Left Receive Buffer Register 0
| LRBRX | The left stereo data received serially from the receive channel input (SDI). If the RX FIFO is full and the two-stage read operation (for instance, a read from the I2S_LRBR0[LRBRX] bit field followed by a read from the I2S_RRBR0[RRBRX] bit field) is not performed before the start of the next stereo pair, then the new data is lost and an overrun interrupt occurs (data already in the RX FIFO is preserved). Note: Before reading this register again, the right stereo data must be read from the I2S_RRBR0[RRBRX] bit field or the status (interrupts) will not be valid. |